IGLOO2 Manuals & User Guides

IGLOO ® 2 Evaluation Kit - Brzi početak rada s karticom Uvod Microchipov IGLOO2 FPGA Evaluation Kit olakšava razvoj ugrađenih aplikacija koje uključuju upravljanje motorom, upravljanje sustavom, industrijsku automatizaciju i brze serijske I/O aplikacije kao što su PCIe, SGMII i korisnički prilagodljivi serijski…

IGLOO2 HPMS AHB Bus Matrix Configuration Introduction The IGLOO2 System Builder automatically configures the memory mapping for you based on your selections of the memory to be used in the design. No user configuration of memory mapping is necessary. You…

Microsemi IGLOO2 HPMS Single Error Correct / Double Error Detect Introduction The IGLOO2 HPMS has an embedded DDR controller (HPMS DDR). This DDR controller is intended to control an off-chip DDR memory. The HPMS DDR controller can be accessed from…

Microsemi IGLOO2 HPMS DDR Controller Configuration Introduction The IGLOO2 HPMS has an embedded DDR controller (HPMS DDR). This DDR controller is intended to control an off-chip DDR memory. The HPMS DDR controller can be accessed from the HPMS (using HPDMA)…

Microsemi IGLOO2 HPMS DDR Bridge Configuration Configuration Options The HPMS DDR bridge is a data bridge between four AHB bus masters and a single AXI bus slave. It accumulates AHB writes into write combining buffers prior to bursting out to…

Microsemi IGLOO2 SERDES velike brzine 3x oversampling Design User Guide Introduction IGLOO®2 field programmable gate array (FPGA) devices have embedded high speed serial/deserializer (SERDES) blocks that can handle data rates from 1 Gbps to 5 Gbps. Because of internal phase…